1. Field of the Invention
The present invention relates to a memory system having a plurality of types of memory chips and a memory controller for controlling these memory chips.
2. Description of the Related Art
With the progression of semiconductor manufacturing technology and semiconductor design technology, it has become possible to implement one whole system on a single semiconductor chip. A semiconductor that operates as a single system is generally referred to as a system LSI. A system LSI contains, for example, an MPU core for controlling the entire system, peripheral cores (IP cores) having a predetermined function, and a memory core. The memory core stores programs necessary for the operation of the system, data for the system to handle, and so on.
Recently, there have been developed portable apparatuses that handle large amounts of data such as moving images. When these portable apparatuses use memory capacities beyond those of the memory cores mounted on their system LSIs, it is usual to constitute the systems with semiconductor memories (memory chips) externally attached to the system LSIs. The reason for this is that if high capacity memory cores are incorporated into the system LSIs, the system LSIs increase in chip size and might drop in yield.
Furthermore, logic products such as an MPU and memory products such as a DRAM are optimized in design for respective features, and manufactured under respective optimum conditions. Accordingly, designing and manufacturing the memory chips aside from the system LSIs (logic chips) can improve system performance.
FIG. 1 shows an example of the system (memory system) in which a plurality of types of memory chips are externally attached to a system LSI. Here, a memory system refers to a set of functions of a system constituting the above-mentioned portable apparatus or the like that are necessary for memory operation.
The memory system comprises a system LSI 2 and a plurality of types of memory chips 3a, 3b, and 3c to be mounted on a printed-circuit board 1. The system LSI 2 has an MPU 4 for controlling the entire system, peripheral cores (IP) 5a and 5b having a predetermined function, and memory controllers 6a, 6b, and 6c corresponding to the memory chips 3a, 3b, and 3c, respectively. The memory chips 3a, 3b, and 3c are respectively connected to the memory controllers 6a, 6b, and 6c through buses 7a, 7b, and 7c which are laid on the printed-circuit board 1.
Conventionally, in the case of constructing the memory system from the system LSI 2 and the plurality of types of memory chips 3a, 3b, and 3c, it has been required, as described above, that the memory chips 3a, 3b, and 3c be individually provided with the memory controllers 6a, 6b, and 6c. For example, SDRAMs and flash memories have different command systems and operation timing for performing write operations and read operations. Therefore, SDRAM and flash memories have necessitated their respective memory controllers when externally attached to a system LSI. As a result, there has been a problem that the system LSI 2 grows in chip size and increases in chip cost.
Since the terminals of the memory chips 3a, 3b, and 3c are connected to the terminals of the system LSI 2 through the buses 7a, 7b, and 7c, respectively, the number of terminals of the system LSI 2 becomes enormous. Consequently, the system LSI 2 might be greater in chip size depending on the number of terminals. In worst cases, it has been necessary to develop a new package for the number of terminals of the system LSI 2.
Since the plurality of memory controllers 6a, 6b, and 6c are mounted on the system LSI 2, the system LSI 2 has been greater in circuit scale, requiring an enormous amount of time for design verification.
The formation of the buses 7a, 7b, and 7c necessitates large numbers of wires on the printed-circuit board 1. Consequently, there has been a problem that the wiring layers of the printed-circuit board 1 grows in number, increasing the design cost and manufacturing cost of the printed-circuit board 1.
Clock synchronous SDRAMs have been developed to improve the data transmission rates of DRAMs. For other clock asynchronous semiconductor memories (including nonvolatile memories), products of clock synchronous type are also likely to be developed.